1. Field of the Invention
The present invention relates to electronic packages, and, more particularly, to an electronic package with reduced fabrication cost, and a method of fabricating the electronic package.
2. Description of Related Art
As the electronic industry is rapidly advancing, electronic products are required to have multi-functionality and high performance. Accordingly, a variety of packaging techniques are brought to the market, including flip chip type package such as chip scale package (CSP), direct chip attached (DCA) or multi-chip Module (MCM) or 3D chip stacking type package (3D IC).
FIG. 1 is a cross-sectional view showing a method of fabricating a semiconductor package 1 of a conventional 3D chip stacking type. A through silicon interposer (TSI) 10 is provided. The through silicon interposer 10 has a chip mounting side 10a, a switching side 10b opposing the chip mounting side 10a, and a plurality of through-silicon vias (TSV) 100 coupled with the chip mounting side 10a and the switching side 10b. A redistribution layer (RDL) 101 is formed on the switching side 10b. Electrode pads 190 of the semiconductor chip 19 with smaller spacing are electrically connected onto the chip mounting side 10a via a plurality of solder bumps 102. An underfill 192 encapsulates the solder bumps 102. An encapsulant 18 is formed on the through silicon interposer 10 and encapsulates the semiconductor chip 19. A plurality of conductive elements 103 such as bumps are formed on the redistribution layer 101 and electrically connected with the bonding pads 170 of the package substrate 17 with larger spacing. An underfill 172 encapsulates the conductive elements 103.
A typical method of fabricating the semiconductor package 1 is described as follows. The through silicon interposer 10 having a plurality of recessed portions (not shown) is mounted on a first carrier (such as a wafer, not shown). Then, the conductive elements 103 are received in the recessed portions correspondingly via an adhesive, for positioning the through silicon interposer 10. Subsequently, the semiconductor chip 19 is mounted on the through silicon interposer 10, and is electrically connected with the through silicon interposer 10 via the solder bumps 102. A second carrier (not shown) is then attached to the semiconductor chip 19, followed by a chip-flipping process, and then the first carrier and the adhesive is removed. After the chip-flipping process is performed, the through silicon interposer 10 is attached to the package substrate 17 via the conductive elements 103, followed by removing the second carrier and the adhesive, and then the encapsulant 18 is formed.
However, the method of fabricating the semiconductor package 1 requires that the carrier and the adhesive be attached and removed and the flipping process be performed many times. The method is thus complicated, and the semiconductor package 1 fabricated has a high cost.
Thus, there is an urgent need for solving the foregoing problems.